From silicon crystal growth to EUV lithography: end-to-end wafer fabrication and the physical–engineering foundations of ASML scanners

Abstract

Advanced integrated-circuit manufacturing relies on a tightly coupled process chain that starts with a monocrystalline silicon wafer and culminates in nanoscale pattern transfer by photolithography. This doctoral-level treatise provides a technical–academic review of silicon wafer manufacturing and the physical–engineering foundations of extreme ultraviolet (EUV, 13.5 nm) lithography as implemented in ASML scanners. The workflow is presented from purification and crystal growth (Czochralski and Float-Zone), through geometric and surface conditioning (sawing, lapping, etching, polishing, and cleaning) and metrology-driven specifications (orientation, roughness, doping, resistivity), to the EUV ecosystem: tin-plasma laser-produced light sources, fully reflective optics, Mo/Si multilayer reticles, pellicles, vacuum operation, contamination control, ultra-precision mechatronics, and overlay budgets. Fundamental and practical limits—photon shot noise, resist stochasticity, line-edge roughness, mask defectivity, and flare—are discussed, and technology roadmaps from 0.33-NA NXE systems to 0.55-NA High-NA EXE platforms are synthesized in terms of resolution, process simplification, and productivity. The manuscript integrates resolution models, photon energy (~92 eV), and EUV photon–matter interaction mechanisms in resists, emphasizing the trade-offs that govern Q2/Q1 manufacturing nodes.